Senior Silicon Architect

About The Job

The US base salary range for this full-time position is $218,000 - $237,000 + 15% bonus target + equity + benefits determined by role, level, and location. Individual pay is determined by additional factors, including job-related skills, experience, and relevant education or training.

Responsibilities

• Lead the definition of chip IP architectures, memory hierarchy, interconnect fabrics, and IP integration to meet product requirements.
• Utilize high-level performance and power models to guide architectural decisions and conduct detailed trade-off analyses to optimize for system-level goals.
• Create and maintain detailed architectural specification documents that guide micro-architecture and design teams throughout the project lifecycle.
• Collaborate with software, product management, and physical design teams to ensure the hardware architecture is feasible, aligns with software needs, and meets all product requirements.
• Drive the technical evaluation, selection, and integration strategy for key third-party IP cores and technologies.
• Research emerging technologies and industry trends to influence and contribute to the long-term silicon and system architecture roadmap.

Requirements

• 4 years of experience in Microarchitecture design such as pipelines, caches, TLBs, execution systems, memory;
• 4 years of experience in System-level optimization or SoC-level optimization such as performance, power, reliability, cost;
• 4 years of experience in IP integration or Silicon IP integration for System-on-Chip (SoC) designs;
• 4 years of experience in RTL code analysis such as Verilog or VHDL;
• 4 years of experience in Technical leadership such as project planning and driving decisions with stakeholders;
• 1 year of experience in Machine Learning (ML) accelerator architecture design.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering or a related field.

Skills

• Experience in Microarchitecture design such as pipelines, caches, TLBs, execution systems, memory;
• Experience in System-level optimization or SoC-level optimization such as performance, power, reliability, cost;
• Experience in IP integration or Silicon IP integration for System-on-Chip (SoC) designs;
• Experience in RTL code analysis such as Verilog or VHDL;
• Experience in Technical leadership such as project planning and driving decisions with stakeholders;
• Experience in Machine Learning (ML) accelerator architecture design.

Benefits

• Google offers a comprehensive benefits package including health insurance, retirement plans, and paid time off.

Pay

• The US base salary range for this full-time position is $218,000 - $237,000 + 15% bonus target + equity + benefits determined by role, level, and location.

Schedule

• This position may allow for a hybrid schedule as per Google policy.