Senior SerDes Analog Design

About the role

SerDes analog designer focusing 100Gbps+ wireline technologies (TX and RX path). The successful candidate will develop cutting-edge circuits and architectures for ultra-high speed wireline communication systems, driving the development of high performance transistor level design from initial specification through design and layout supervision, silicon evaluation and characterization to final product introduction to market. At Omni Design, we have created an exciting environment with amazing talent across multiple disciplines. We like self-motivated individuals, we encourage initiative, we look for leadership qualities, we value teamwork, we like diversity, and we reward excellence. We are looking for trailblazers to bring Omni Design’s vision to fruition.

Responsibilities

• Develop cutting-edge circuits and architectures for ultra-high speed wireline communication systems (TX and RX paths).
• Drive the development of high performance transistor level design from initial specification through design, layout supervision, silicon evaluation and characterization to final product introduction.
• Work with customers to define products that address their needs.
• Evaluate silicon on the bench using standard lab equipment.
• Work independently, create and adhere to schedules.
• Possess strong written and verbal communication skills and ability to work with teams spread across geographic locations.

Qualifications

• 10+ years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processes.
• Familiarity with high-speed analog design and building block circuits for SERDES technology such as ADC/DAC, CTLE, CDR, PLL, etc.
• Track record of successfully taking designs to production.
• Ability to work with customers to define products that address needs.
• Experience evaluating silicon on the bench and familiarity with standard lab equipment.
• Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis.
• Experience with analog and digital behavioral modeling, and/or synthesis of digital control blocks.
• Familiarity with Cadence schematic capture, Virtuoso, Spectre and/or HSPICE circuit simulation tools.
• MATLAB understanding preferred but not mandatory.
• Familiar with designing circuits for electromigration and ESD compliance in submicron CMOS processes.
• Familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processes.
• Ability to work independently, create and adhere to schedules.
• Strong written and verbal communication skills with ability to work with teams across geographic locations.