Senior RTL Design Engineer - CPU Frontend

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms enable leading technology companies to innovate, optimize, and deliver advanced solutions across markets such as artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

Our constant innovation and success are driven by our talented teams, who collaborate to develop groundbreaking ideas and solutions that impact people's lives—making the world a better place, one processor at a time.

Responsibilities

• Architect, design, and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
• Perform initial sandbox verification and work with the design verification team to create and execute thorough verification test plans.
• Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
• Collaborate with the performance modeling team for performance exploration and optimization to meet performance goals.
• Develop and specify microarchitecture.
• Ensure knowledge is shared via great documentation and participation in a culture of collaborative design.

Requirements

• BS/MS degree in computer science, computer engineering, electrical engineering, or related field, or equivalent experience.
• 3+ years of design experience.
• Academic or professional experience with CPU RTL design in one or more of the following areas: instruction fetch, instruction decode, branch prediction, coherent caches, cache prefetching, TLBs.
• Proficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL.
• Strong software engineering skills/background, including:
  • Object-oriented, aspect-oriented, and particularly functional programming.
  • Templated metaprogramming, in any language.
  • Compiler infrastructures, particularly for domain-specific languages.
  • Data modeling, particularly intermediate representations for optimizing or transforming compiler passes.
  • Test-driven development, particularly ability to write adaptive unit tests.
• Attention to detail and a focus on high-quality design.
• Ability to work well with others and share the belief that engineering is teamwork.

Nice-to-haves

• Experience with Scala/Chisel, Bluespec, or some other language/DSL for expressing configurable hardware via software.
• Knowledge of RISC-V architecture.
• Expertise in CPU processor designs in one or more of the following areas: instruction fetch; instruction decode; register renaming and instruction scheduling; vector units; load-store unit.
• Knowledge of verification principles, testbenches, UVM, and coverage.
• Experience with Git/Github, Jira, Confluence.

Pay

We have a market-based pay structure which varies by location. The base pay range is a guideline, and compensation depends on job-related knowledge, skills, and relevant work experience. The range provided reflects the cost of labor in the U.S. geographic market based on the location of the role.

Base Pay Range: $158,760.00 - $194,040.00

In addition to base pay, this role may be eligible for variable/incentive compensation and/or equity.

Benefits

This role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more.