Senior Principal Engineer, Design Verification

About the Role

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. The Custom Silicon Engineering team provides custom solutions for high performance compute, server, network processing, and storage applications. CCS&A products employ state-of-the-art custom and industry standard technologies such as CXL, PCIE, Ethernet, and ARM CPU cores.

Responsibilities

• Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers using System Verilog and UVM methodology.
• Analyze designs and architectures to develop test strategies that will ensure functional correctness.
• Develop verification testplan and write tests using random techniques and coverage analysis, and work with designers to ensure it is complete.
• Debug failures and work with designers to resolve issues.
• Contribute and drive the development and future direction of SoC verification methodologies and environments.
• Independently propose and define new high-level technical work.
• Provide leadership for a geographically dispersed team of verification professionals in pre-silicon validation of a highly complex SoC design.

Requirements

• Bachelor’s degree in Electrical Engineering, Electronics, Computer Engineering, or related fields with 15+ years of experience.
• Master’s degree and/or PhD in Electrical Engineering, Electronics, Computer Engineering, or related fields with 10+ years of experience.
• PhD in Electrical Engineering, Electronics, Computer Engineering, or related fields with 8+ years of experience.
• Strong experience in architecture and implementation of complex/random verification testbench environments using System Verilog/UVM.
• 10+ years of direct hands-on verification experience at block, subsystem, and full chip level contexts.
• Technical leadership experience in driving SoC teams with multi-domain technical expertise for validating SoCs.
• Strong experience with developing and executing detailed verification test-plans with coverage.
• Extensive experience with scripting languages such as Python or Perl and EDA verification tools, as well as bug tracking and regression mechanisms.
• Expertise in cross-functional collaboration for driving outcomes and participating in problem-solving and quality improvement activities.
• Expertise in guiding and mentoring technical teams for successful execution.
• Ability to generate ideas, take up initiatives, and drive verification productivity gains.
• Must have the ability to define problems, issues, and opportunities, analyze data, establish facts, and draw valid conclusions from various datasets.
• Must have the ability to multi-task in a fast-paced environment.

Pay

Expected Base Pay Range (USD): $204,900 - $303,250 per annum. The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location, and market conditions.

Benefits

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage—from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include:

• An employee stock purchase plan with a 2-year look back.
• Family support programs to help balance work and home life.
• Robust mental health resources to prioritize emotional well-being.
• Recognition and service awards to celebrate contributions and milestones.