Senior Engineer, Design Verification
About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Group Description
Marvell's CXL Product Development team works on groundbreaking innovations for the composable datacenter. We are looking for individuals with a deep understanding and passion for ASIC verification to craft creative solutions for DV architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. If you're creative and autonomous, we want to hear from you!
What You Can Expect
- Develop verification plans for complex designs.
- Verify complex SoCs through simulation of register-transfer level (RTL) and gate level designs using industry standard tools and processes.
- Collaborate closely with design and other verification engineers to develop and implement verification test plans and drive verification methodology work.
- Develop constrained-random verification test environment using Verilog/System Verilog, UVM and C programming, including testbenches, checkers, monitors, drivers and other testbench components.
- Use problem solving skills to debug failing simulations and create test vectors and testing scenarios to exhaustively exercise a design.
- Drive and analyze test coverage metrics.
What We're Looking For
- BS in Electrical/Computer Engineering with 2 years of relevant experience
- Or MS in Electrical/Computer Engineering
- Must have work/internship experience or completed graduate coursework/research in each of the following:
- Synopsys VCS (simulation)
- Synopsys Verdi (debugging and waveform analysis)
- Verilog, SystemVerilog, UVM
- C/C++ and Python scripting
- RTL Design Debug
- Functional Verification, Assertion-Based Verification, Constrained Random Verification
- AMBA AXI4 Protocol
- PCIe fundamentals
- Developing test plans and coverage models
- Advanced Computer Architecture concepts
Expected Base Pay Range
The expected base pay range for this role is $97,700 - $144,410 per annum. The expected base pay range may be modified based on market conditions.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.