Senior Design Verification Engineer

About The Role

Intel is seeking a Senior Design Verification Engineer for the Silicon Chassis team. In this role, you will own end-to-end verification of critical chassis and interconnect IP blocks from planning through signoff. You will drive quality in testbench architecture, test plan and coverage closure while working closely with architecture, design, and software teams.

Responsibilities

• Own verification planning and execution for key IP features across IP and subsystem integration points
• Build scalable verification environments and targeted test plans with reusable test benches, checkers, VIPs, and behavioral models
• Collaborate closely with architecture, design, and software teams from specification through bringup; contribute across role boundaries when needed to unblock progress and maintain execution quality
• Drive ownership of multiple critical blocks and verification components; take full responsibility for functional signoffs and achievement of performance and power metrics
• Lead IP delivery to multiple customers while ensuring technical excellence; balance competing requirements, schedules, and resources across teams
• Drive convergence of simulation and formal verification into unified bug hunting and coverage closure strategies; evaluate and adopt emerging methodologies including ML-driven verification flows
• Mentor and develop verification engineers; establish verification best practices and raise team-level execution quality
• Comfortable using AI-assisted development tools as part of everyday workflow; track record of delivering reusable, configurable verification collateral

Qualifications

• Bachelor of Science Degree in Electrical or Computer Engineering, Computer Science, or in a STEM related field
• 10+ years of experience in design verification (DV); with extensive background in IP DV, and subsystem and SoC-level verification
• Experience in interconnects, caches, and memory subsystems, including multiple bus protocols such as AMBA (CHI, ACE, AXI), PCIe, UCIe, and CXL; cache coherency and memory consistency models
• Experience in verification of global functions including debug, trace, clock and power management, RAS, QoS, and security feature
• Experience in simulation and formal verification methodologies including UVM, SVA, ABV, and co-simulation; proficiency in low-power verification techniques, HDL/verification languages, and industry-standard EDA tools
• Hands-on coding experience across SystemVerilog/UVM, C/C++, Python, and build systems
• Experience working with RTL, physical design, and CAD tool flows; contribute outside core DV responsibilities as needed