Senior Manager, Mixed-Signal and Systems Validation

About the Role

We are seeking a highly technical Senior Manager to lead a world-class engineering team responsible for the post-silicon validation, mixed-signal IP verification, and system-level testing of next-generation Hard Disk Drive (HDD) Read Channels and advanced AI ASICs. In this role, you will bridge the gap between silicon design and system deployment.

Responsibilities

Team Leadership & People Management

• Manage and mentor a talented team of validation and system integration engineers, fostering a culture of innovation, accountability, and continuous growth.
• Oversee project scheduling, resource planning, and budget management to ensure milestones are met on time and within scope.
• Partner closely with ASIC Design, Architecture, Firmware, and Product Engineering teams to align on validation requirements and resolve complex technical issues.

HDD Read Channel & AI ASIC Validation

• Define and execute comprehensive pre-silicon and post-silicon validation plans for complex HDD Read Channels and high-performance AI ASICs. Pre-silicon validation is accomplished with Palladium and Zebu emulators; post-silicon validation is on the ASICs using test systems designed for the devices.
• Lead the bring-up, characterization, and debugging of new silicon in the lab, identifying and root-causing hardware and architectural flaws.
• Drive the development of scalable, automated test infrastructure and methodologies to improve test coverage and execution efficiency.

Requirements

Education & Experience

• Master’s (MS) or Ph.D. in Electrical Engineering, Computer Engineering, or a closely related technical field.
• 15+ years of experience in read channel/HDD design/validation, post-silicon validation, mixed-signal IC characterization, or system engineering.
• 5+ years managing a technical team of engineers.
• Proven track record of managing, leading, and building high-performing technical engineering teams.

Technical Expertise

• Deep understanding of HDD architectures, signal processing, and Read Channel technologies and systems validation.
• Strong technical understanding of ADCs, PLLs, Continuous-Time Filters, and closed-loop feedback systems.
• Understanding of AI/ML ASICs and accelerators.
• Strong expertise in System-Level Testing (SLT), board-level debugging, and lab equipment (oscilloscopes, logic analyzers, protocol analyzers).
• Proficient in test automation languages (e.g., Python, MATLAB) and lab equipment automation.
• Strong data analysis skills to interpret complex silicon characterization data.

Leadership Competencies

• Excellent communication and presentation skills, with the ability to translate complex technical concepts for executive leadership and stakeholders.
• Strong problem-solving skills and a data-driven approach to debugging and decision-making.

Pay

The annual base salary range for this position is USD 167,500.00 to USD 268,000.00.

Benefits

• Discretionary annual bonus and opportunity to receive new hire equity grant, as well as annual equity awards.
• Comprehensive benefits package including medical, dental, and vision plans.
• 401(K) participation with company matching.
• Employee Stock Purchase Program (ESPP).
• Employee Assistance Program (EAP).
• Paid holidays, sick leave, and vacation time.
• Compliance with all applicable laws for Paid Family Leave and other leaves of absence.