Mixed Signal validation engineer

About the role

This role requires regular onsite presence to fulfill essential job responsibilities. The position involves defining, developing, and performing pre-silicon functional validation for mixed signal design, electronic parts, components, or integrated circuitry required for mixed signal electronic equipment, devices, and other hardware systems.

Responsibilities

• Define, develop, and perform pre-silicon functional validation for mixed signal design, electronic parts, components, and integrated circuitry.
• Apply hardware and software level tools and techniques to ensure validation coverage and that performance, power, and area goals are met.
• Review proposed design changes to assess impact on validation plans, tasks, and timelines.
• Develop mixed signal validation methodologies, execute validation plans, and collaborate with other engineers for design optimization, troubleshooting, and failure analysis.
• Perform debug to identify root causes and resolve all functional and triage failures for mixed signal design issues.
• Test interactions between various mixed signal design features using validation infrastructure.
• Develop pre-silicon validation infrastructure (e.g., monitors, behavioral checkers, coverage) and test environments used in validation testing.
• Publish mixed signal validation reports summarizing all validation activities performed, review results, and communicate findings to relevant teams.
• Work with architecture, design, verification, board, platform, and manufacturing teams to maintain and improve debug, validation test strategy, methodologies, and processes for mixed signal interfaces to meet desired product specifications.

Requirements

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

• Bachelor’s Degree in Computer Science, Computer Engineering, Electrical Engineering, or another STEM-related degree with 3+ years of experience, OR
• Master’s Degree in Computer Science, Computer Engineering, Electrical Engineering, or another STEM-related degree with 6+ months of experience.
• Experience working on IP or SoC development, verification, or integration using System Verilog/OVM/UVM.
• Experience writing validation plans and implementing those validation plans using System Verilog.

Skills

• Preferred: 2+ years of experience with DFI/DDR/LPDDR Protocols.
• Preferred: 2+ years of experience with DDR Phy verification or Memory Controller verification.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Pay

Annual Salary Range for jobs which could be performed in the US: $122,440.00 - $172,860.00 USD. The range displayed reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.

Schedule

This role follows Shift 1 (United States of America) and is eligible for our hybrid work model, allowing employees to split their time between working on-site at their assigned Intel site and off-site.