Mixed Signal Verification Engineer

Responsibilities

• Create and maintain AMS/DMS testbenches for wireless RF and high-speed PHY designs.
• Partner with RF and Analog Design Engineers to develop and validate analog circuit models.
• Develop Real Number Models (RNM) for mixed-signal verification.
• Perform digital and mixed-mode simulations and debug verification failures.
• Develop and execute verification environments using SystemVerilog and UVM.
• Analyze simulation results and perform waveform debugging.
• Support silicon bring-up, validation, and commercialization activities.
• Collaborate with cross-functional design, verification, and validation teams.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of relevant verification or mixed-signal engineering experience.
• Strong understanding of digital VLSI simulation flows.
• Strong knowledge of mixed-mode and analog simulation flows.
• Hands-on experience with Verilog/SystemVerilog.
• Experience developing RNM/real-number models.
• Experience with UVM-based digital verification and waveform debugging.
• Strong analytical, troubleshooting, and communication skills.
• Able to work effectively within cross-functional engineering teams.

Preferred Qualifications

• Experience with wireless RF transceiver architectures.
• Knowledge of SerDes and high-speed PHY technologies.
• Experience with AMS/DMS verification for complex SoC or semiconductor designs.
• Familiarity with analog behavioral modeling and mixed-signal verification methodologies.