Sr. Mixed Signal Design Verification Manager

About the Role

Qorvo’s fast-growing Power Management division, focused on Power loss protection, PMICs, Motor Control, and Battery Management solutions for a wide range of Mobile, Consumer, IoT and Industrial applications, is seeking an experienced Top-level Design Verification Engineer to create next-generation and world-class designs in power management solutions.

Responsibilities

• Manage and grow a team of verification engineers with different levels of experience, from entry level to senior principal level.
• Drive technical direction and strategy for verification excellence.
• Serve as customer-facing for catalog and custom power-management ICs including motor driver, power-loss protection, point of load, and battery management IC solutions.
• Develop and execute metric-driven design verification plans based upon IC functional, performance, and test specifications, with a strong focus on the customer use-case.
• Develop constrained random tests and automated checkers within our TLDV UVM environment.
• Build high performance, accurate RNM, or VerilogAMS models to support TL simulation.
• Collaborate with design team to resolve issues identified during verification.
• Partner with internal design and test teams to ensure device first-pass testability.
• Continuously improve and align verification methodologies with industry best practices.
• Automate verification tasks where applicable.

Requirements

• Bachelor’s degree in electrical engineering or a related field, with strong focus on mixed-signal circuit design and verification.
• 15+ years of experience or an equivalent amount of advanced education and experience in AMS design or verification of analog and power-management ICs.
• Experience managing or being a functional team lead.
• Strong technical background with hands-on experience in UVM, analog and digital design fundamentals, and system-level knowledge of power management ICs.
• Excellent problem-solving and debugging skills.
• Effective communication and collaboration skills.
• Expertise in mixed-signal concepts such as Spice/Spectre and event-based simulator, co-simulation environment, simulation debug, silicon debug.

Preferred Qualifications

• Master’s degree in electrical engineering or a related field, with strong focus on mixed-signal circuit design and verification.
• Experience in Top-Down Design Methodology.
• Proficiency in shell or Python scripting.
• Familiarity with SV-UDN/EENET modeling techniques.
• Experience with both GUI and command-line simulation flows.
• Proficiency with SV Assertions and Functional coverage.
• Understanding integration of AI into a verification workflow.

Other

10% or less domestic or international travel may be required.