Mixed Signal Systems and Verification Engineer II

Responsibilities

• Be part of a hands-on development team that promotes engineering excellence, creativity, and innovation.
• Develop accurate, simulation-efficient analog and mixed-signal behavioral models (RNM) in SystemVerilog.
• Verify that behavioral models accurately represent analog schematics and design intent.
• Integrate analog behavioral models with RTL environments.
• Verify analog and mixed-signal functionality against specifications using: SystemVerilog testbenches, Test scenarios, Assertions, including Analog Assertion-Based Verification.
• Support verification of blocks such as filters, ADC/DAC, VCO, A/DPLL, SerDes, LNA, mixers, and related AMS IP.
• Debug verification failures across analog, digital, and mixed-signal domains.
• Develop and maintain verification infrastructure including testbenches, environments, and scripts.
• Document modeling assumptions, verification methodology, and results for formal design and verification reviews.
• Collaborate cross-functionally with design, systems, and IP teams to understand constraints and ensure verification coverage.

Required Qualifications

• 0–2+ years of experience working in digital, analog, or mixed-signal design and verification environments.
• Bachelor’s degree in Electrical Engineering or related field (MSEE or PhD preferred).
• Strong understanding of SystemVerilog and mixed-signal verification concepts.
• Experience or coursework in real-number modeling (RNM) including: wrealUDN / UDT / UDR, Verilog-AMS, Basic understanding of analog and mixed-signal blocks such as ADCs, DACs, PLLs, SerDes, RF or signal-processing components.
• Familiarity with Cadence Virtuoso Schematic Composer and ADE.
• Strong written and verbal communication skills with the ability to work across teams.
• Comfortable working in a fast-paced, collaborative development environment.

Preferred Qualifications

• Experience developing verification infrastructure (testbenches, environments, automation).
• Experience scripting verification and design automation flows using Python or Perl.
• Experience with low-power architectures.
• Exposure to SystemVerilog UVM methodologies.
• Experience with FPGA prototyping.
• Exposure to hardware acceleration platforms such as Palladium or Protium.
• Experience with revision control systems (e.g., SOS, SVN).