Senior Mixed Signal Design Validation Engineer

About the role

Join NVIDIA’s high-speed mixed-signal circuits team as a Mixed Signal Design Validation Engineer and lead the bring-up and characterization of complex memory interfaces. You will validate high-speed I/O systems, focusing on LPDDR, GDDR, and HBM memory technologies to ensure the highest standards of quality and reliability for NVIDIA’s pioneering GPUs and AI computing platforms.

Responsibilities

• Lead and drive the creation of validation test plans and test scripts for DDR I/O associated with LPDDR, GDDR, and HBM memory interfaces, ensuring coverage of all required analog and digital circuits.
• Conduct thorough characterization of analog, digital, and mixed-signal circuit blocks under varying conditions (process, voltage, temperature) and correlate results with simulations.
• Drive system-level validation for memory interfaces, ensuring high-speed performance and quality metrics meet demanding GPU and AI system standards.
• Investigate memory I/O circuits to identify weaknesses and pave the way for circuit improvements and architectural enhancements in future products.
• Lead debugging efforts and design creative solutions to resolve unexpected bugs.
• Validate silicon performance, quality, and margins to refine memory interface designs.
• Develop and implement test scripts to optimize DDR I/O circuits, sub-circuits, and overall system performance.
• Work closely with multi-functional teams, including mixed-signal design, PISI, hardware, firmware, and memory qualification engineers, to resolve issues and improve memory interface performance.
• Develop and implement tools and scripts to enhance electrical characterization and chip bring-up processes.
• Mentor and train new engineers on validation practices, fostering a culture of excellence and continuous improvement.

Requirements

• A BS degree or equivalent experience with 8+ years in Electrical Engineering, Computer Engineering, or a related field.
• Solid experience in silicon bring-up and debugging, particularly for high-speed memory interfaces.
• Strong understanding of memory systems and specifications.
• In-depth technical knowledge of mixed-signal circuits, analog, and digital systems, with a focus on high-speed memory technologies.
• Strong knowledge of signal integrity and power integrity.
• Experience with lab instrumentation such as oscilloscopes, logic analyzers, spectrum analyzers, TDR, phase noise analyzers, signal generators, and BER testers.
• Strong scripting skills in Python, C, or similar languages, with experience in Git and JMP for version control and data analysis.
• Ability to work in a fast-paced, dynamic environment involving multiple chip bring-ups and system validations.
• Collaborative mindset to work effectively with cross-functional teams.
• Strong problem-solving skills with a proactive and forward-thinking approach.

Skills to stand out

• Expertise in measurement theory and the use of test instruments, especially for memory interface validation.
• Knowledge of other high-speed transceiver performance.

Pay

Base salary range: $168,000 – $264,500 USD (Level 4) or $196,000 – $310,500 USD (Level 5), depending on location, experience, and comparable roles. Eligible for equity and benefits.