Senior FPGA Engineer

About the role

The Senior FPGA Engineer will play a critical role in the design and development of advanced FPGA solutions supporting cutting-edge space-based electronic systems. This position is responsible for architecting, implementing, and verifying complex high-speed programmable logic designs for Software Defined Radios (SDRs), On-Board Processors (OBPs) and storage solutions using the latest AMD (Xilinx) technologies.

Responsibilities

• Create and maintain complete FPGA designs using a combination of VHDL and Vivado IP Integrator with a strong emphasis on efficient data path architecture, reliable timing closures, and high-performance implementations
• Code, simulate and verify a wide range of RTL modules for FPGAs including modules for digital signal processing (DSP), control algorithms, interfaces to external peripherals, etc.
• Create and maintain comprehensive simulation test bench modules to ensure a high degree of code coverage and verify functionality of firmware modules
• Create and maintain Timing Constraints to ensure design is fully constrained and consistent
• Timing Results are achieved post-implementation
• Design and implement solutions that use embedded ARM processors, DDR4 memory, high-speed serial interfaces such as Aurora, JESD204B/C, PCIe, 1G/10G/100G Ethernet, etc.
• Participate in code reviews, design reviews, and contribute towards FPGA Design methodologies and best practices
• Work in close collaboration with hardware and software engineers throughout the integration process to ensure that FPGA designs are correctly implemented
• Mentor junior engineers: provide training, guidance, and support as needed
• Ability to support travel or off-site work, as needed

Requirements

• Bachelor’s degree in Computer Engineering, Electrical Engineering or related technical degree
• 6+ years of related experience with a bachelor’s degree OR a 4+ years of experience with a master’s degree
• Experience with firmware design, simulation and verification
• Thorough understanding of FPGA design methodology including physical synthesis, static timing analysis, place/route, verification, power analysis, and timing closure techniques
• Experience designing with Xilinx SoC/FPGA devices using the Vivado Design Suite
• Experience using Vivado IP Integrator
• Experience with RTL logic design and coding using VHDL
• Experience writing simulation testbenches to identify bugs and verify designs using SystemVerilog
• Experience with board bring-up/verification in an electronic lab environment and use of FPGA ILA-based debugging tools such as Vivado HW Debugger, Chipscope, SmartDebug

Preferred Qualifications

• Experience programming and implementing designs using the Versal AI Engines
• Experience designing with Microsemi (Microchip) FPGAs using Libero
• Experience using revision control systems, such as Git
• Experience using Modelsim/Questasim and/or Aldec simulation tools
• Familiarity with lab test equipment such as logic analyzers, oscilloscopes, signal generators, spectrum analyzers, etc.
• Experience with DSP MATLAB and Simulink
• Experience with Linux, C/C++