Senior FPGA Design Engineer (Nextest, Tualatin, OR)

Opportunity Overview

Teradyne’s Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions. MTD creates advanced solutions for complex testing applications, driving innovation through creativity and diverse perspectives. Our test instrumentation supports the world’s most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery.

We are looking for an FPGA Design Engineer with exceptional technical skills and a strong desire to collaborate on team-oriented projects. Success in this role means delivering high-quality, reliable products to market quickly. If you are excited to join a dynamic, global team, Teradyne may be the place for you!

About the Role

Architect and implement FPGA solutions to support next generation Flash and DRAM test instrumentation. Provide technical guidance to junior engineers Turn abstract concepts and customer requirements into reliable, extensible, and supportable designs. Assist in the maintenance and extension of existing FPGA designs to support quality improvement and emerging customer requirements. Maintain schedule commitments and deliver high quality end products.

Responsibilities

• Architect and implement FPGA solutions to support next generation Flash and DRAM test instrumentation.
• Provide technical guidance to junior engineers.
• Turn abstract concepts and customer requirements into reliable, extensible, and supportable designs.
• Aid in the maintenance and extension of existing FPGA designs to support quality improvement and emerging customer requirements.
• Maintain schedule commitments and deliver high quality end products.

Requirements

• Bachelor’s Degree or equivalent in Electrical Engineering or a closely related field with a minimum of 5 years of relevant work experience, or Master’s Degree or equivalent with a minimum of 3 years of relevant work experience.
• Experience with Digital Design and Architecture RTL coding, synthesis, timing closure and lab validation.
• Experience with Static Timing Analysis of ASICs or FPGAs.
• Experience with digital simulation testbench creation.
• Familiarity with lab equipment such as oscilloscopes, power supplies and waveform generators.

Qualifications

• Experience with C or C++.
• Familiarity with lab equipment such as oscilloscopes, power supplies and waveform generators.

Skills

• FPGA Transceiver based design experience.
• Experience with DRAM and Flash Memory interfaces.
• Experience with Altera/AMD FPGA tool flows.
• Proficiency with Verilog HDL Language.
• Familiarity with UVM Methodology.
• Scripting languages experience.
• Linux and Windows operating systems experience.

Benefits

Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.