Senior FPGA Design Engineer

About the role

We are seeking a Senior FPGA Design Engineer with over 8 years of experience to lead the development, implementation, and verification of high-speed FPGA solutions. This role requires expertise in high-bandwidth interfaces, such as PCIe Gen4/5, 10 to 100G+ Ethernet, and DDR4/DDR5. The candidate will excel in RTL design using VHDL/Verilog/SystemVerilog and will be responsible for driving FPGA design from concept through production, optimizing for low latency and high throughput, and ensuring compliance with reliability standards. The position is 100% onsite in Greenville, SC, a Contract to Hire role, with cubicle‑based workspaces and a small test lab. The team culture is diverse, with some individuals enjoying social activities after work, while others focus more on family‑oriented engagements.

Responsibilities

• Lead full life-cycle FPGA development, from requirements and architecture through RTL implementation, verification, and system integration across multiple FPGA families.
• Define and document FPGA architecture, including block diagrams and clocking strategies, and conduct design reviews.
• Develop robust and reusable testbenches and achieve code coverage closure.
• Create and execute detailed test plans, procedures, and reports to ensure verification rigor.
• Collaborate with hardware and software teams to integrate FPGA designs at the board and system level.
• Implement and validate JTAG boundary scan and other DFT features, ensuring compliance with design-for-test standards.
• Drive continuous improvement in design practices and mentor junior engineers.

Requirements

• Strong proficiency in RTL design using Verilog/VHDL.
• Experience in testbench development and verification of complex FPGA designs.
• Proficient with FPGA simulation and synthesis tools such as Xilinx Vivado and Intel Quartus.
• Proficiency in FPGA architecture and optimization techniques.
• Ability to perform FPGA power estimation and analysis.
• Strong understanding of high-speed interfaces and control protocols.
• Experience with System-on-Chip technologies.
• Secret Clearance.

Qualifications

• Proficiency in FPGA Block Design development and debugging.
• Familiarity with Universal Verification Methodology (UVM).
• Familiarity with revision control systems and scripting for automation.
• Skilled in FPGA lab validation using oscilloscopes and protocol analyzers.
• Strong communication skills and experience collaborating in Agile environments.
• Understanding of formal verification processes and compliance standards.

Benefits

• Medical, dental & vision
• Critical Illness, Accident, and Hospital
• 401(k) Retirement Plan – Pre-tax and Roth post-tax contributions available
• Life Insurance (Voluntary Life & AD&D for the employee and dependents)
• Short and long-term disability
• Health Spending Account (HSA)
• Transportation benefits
• Employee Assistance Program
• Time Off/Leave (PTO, Vacation or Sick Leave)

Pay

The pay range for this position is $75.00 - $90.00/hr. Individual compensation offered for this position within this range will depend on many factors, including qualifications, skills, relevant experience, job knowledge, geographic location, internal equity, and other pertinent job-related factors.

Schedule

The schedule includes a 9/80 work arrangement, providing every other Friday off.