Senior ASIC Design Engineer - DFX

About the role

Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.

Responsibilities

• Own the architecture and design of fuse controller and other DFT IPs for cutting-edge SoC designs.
• Develop, deploy, and enhance DFT methodologies for scalability and future product needs.
• Define and align feature sets by working closely with architects, platform, and software teams.
• Partner with design, verification, synthesis, timing, and backend teams to ensure cohesive integration.
• Create and execute test plans to support both functional and DFT full-chip verification.
• Support post-silicon bring-up and validation efforts including debug and issue resolution.
• Mentor junior engineers on test design strategies and trade-offs related to cost, quality, and performance.

Requirements

• Bachelors degree (or equivalent experience) with 8+ years of experience, or Master’s degree in Electrical Engineering or related field with 6+ years experience.
• 5+ years of hands-on experience in SoC architecture, RTL design, and verification.
• Strong proficiency in micro-architecture and RTL development using Verilog. (UVM experience is a plus.)
• Deep expertise in DFT design, methodology, and implementation.
• Familiarity with related domains such as clocking, STA, place & route, and power optimization.
• Experience in post-silicon bring-up on ATE, including understanding of pattern formats, test program development, and failure analysis.
• Proficiency in scripting languages such as Python, Perl, or Tcl.
• Excellent communication skills and a collaborative mindset—with a curiosity and passion for solving complex technical challenges.

Qualifications

• BS in Electrical Engineering or related field with 8+ years of experience.
• MS in Electrical Engineering or related field with 6+ years of experience.

Skills

• Micro-architecture and RTL development using Verilog.
• UVM experience (preferred).
• DFT design, methodology, and implementation.
• Related domains such as clocking, STA, place & route, and power optimization.
• Post-silicon bring-up on ATE.
• Scripting languages such as Python, Perl, or Tcl.
• Excellent communication skills and collaborative mindset.

Benefits

NVIDIA offers competitive compensation, comprehensive benefits, and meaningful opportunities to advance your career. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits.

Pay

Base salary range: 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.

Schedule

Not specified.