Senior ASIC Design Engineer

About the role

This role offers a chance to create real impact in a dynamic, tech-driven company. The products range from consumer graphics to self-driving cars and the fast-growing field of artificial intelligence. Our team consists of outstanding people worldwide, working to push the boundaries of what is possible today and define the future of computing.

Responsibilities

• Micro-architecture and build implementation of NOC/interconnect Xbar.
• Micro-architect features to meet area, performance, and power requirements.
• Deliver a fully verified build by working closely with verification engineers.
• Deliver a synthesis/timing clean build to ensure a routable and physically implementable design.
• Collaborate with architects, verification engineers, software engineers, and physical build engineers to accomplish your goals.

Requirements

• Bachelor's or Master’s Degree in Electrical Engineering or Computer Engineering, or equivalent experience.
• 8+ years of build/RTL experience working on complex units in xbar/memory system.
• Highly proficient in logic design, Verilog and/or System-Verilog, with a solid understanding of Computer Architecture and Digital Systems build.
• A deep understanding of ASIC flow including RTL, verification, logic synthesis, timing analysis, ECO, and post silicon debug.
• Strong interpersonal and communication skills to collaborate across teams.
• Prior experience building arbiters, scheduling, synchronization, bus protocols, interconnect networks and/or switches.
• Familiarity with architecture concepts and implementation of arbitration policies, interconnection routing policies/deadlock avoidance, and virtual channels.
• Good debugging and analytical skills.

Qualifications

• Experience with ASIC flow including RTL, verification, logic synthesis, timing analysis, ECO, and post silicon debug.
• Knowledge of logic design, Verilog and/or System-Verilog.
• Understanding of computer architecture and digital systems build.
• Experience with NOC/interconnect Xbar design.
• Experience with arbitration policies, interconnection routing policies/deadlock avoidance, and virtual channels.
• Strong collaboration and communication skills.
• Experience with building arbiters, scheduling, synchronization, bus protocols, interconnect networks and/or switches.
• Good debugging and analytical skills.

Skills

• Logic design
• Verilog and/or System-Verilog
• Computer Architecture
• ASIC Flow
• NOC/Interconnect Xbar Design
• Arbitration Policies
• Interconnection Routing Policies/Deadlock Avoidance
• Virtual Channels
• Debugging and Analytical Skills

Benefits

• Base salary range: $168,000 - $264,500 for Level 4, and $196,000 - $310,500 for Level 5.
• Eligibility for equity and benefits.

Pay

• Base salary determined based on location, experience, and the pay of employees in similar positions.

Schedule

• Not specified.

Application Instructions

• Applications accepted at least until May 24, 2026.

Contact Information

• NVIDIA

EEO Statement

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.