Senior ASIC Physical Design Engineer

About the role

The Miniature Device Technologies Group at APL develops highly customized tools and techniques for various missions. We work closely with government sponsors to develop solutions to their most challenging problems using our multi-disciplinary set of capabilities in ASIC, PCB, embedded software, FPGA, and signal processing design.

Responsibilities

• Responsible for all back-end flow aspects, including synthesis, top-level floor-planning, timing analysis and design partitioning to meet timing requirements, SCAN and BIST insertion, and physical verification checks.
• Identify and address back-end issues with the ASIC design team.
• Perform custom physical design as needed, including custom block layouts and top-level modifications.
• Contribute to process selection for new designs, assessing size, power, and availability of design features and IP.
• Contribute to the floorplanning of digital and mixed-signal ASICs.
• Perform timing analysis and design partitioning.
• Insert SCAN and BIST for maximum defect coverage.
• Work with digital designers to debug and address back-end related RTL and gate-level issues.
• Perform all physical verification, including DRC, DRC+, MCD, and LVS.
• Perform custom physical layout.
• Assist with ASIC design environment enhancements and scripting.
• Identify and implement process improvements.
• Build and maintain strong working relationships with cross-functional teams.
• Provide leadership and guidance to junior physical design engineers.
• Collaborate with the team to achieve project goals and objectives.

Requirements

• Possess an Associate’s degree in a technical field, or a combination of equivalent level experience/education/certifications.
• Skilled at using Cadence ASIC design tools for back-end flow implementation.
• Skilled at using Siemens Calibre physical verification tools.
• 6+ years of experience specifically performing back-end ASIC design.
• Able to obtain an Interim Secret level security clearance by your start date and can ultimately obtain a Secret level clearance.

Qualifications

• Experience with custom physical layout in Cadence Virtuoso.
• Skilled at using Siemens ASIC design tools for back-end flow implementation.
• Extensive knowledge and experience in ASIC technology characterization for process selection.
• Active clearance and/or successful completion of single-scope background investigations in the past.