Senior ASIC Physical Design Engineer

Google · Sunnyvale, CA · 5 days ago

On-siteEngineeringFull-time

About the role

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

Responsibilities

Participate in the Physical Design of complex blocks.
Contribute to the design and closure of the full chip and individual blocks from RTL-to-GDS.
Collaborate with internal logic and internal and external teams to achieve the best Power/Performance Analysis (PPA). This includes conducting feasibility studies for new microarchitectures as well as optimizing runs for finished RTL.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
7 years of experience with physical design (e.g. from RTL to GDSII, including key stages like floorplanning, place and route, and timing closure).
Experience in Python, Tcl, or Perl scripting.

Preferred qualifications

Experience working with external partners on Physical Design (PD) closure.
Experience in Static Timing Analysis (STA), with an understanding of how to define timing corners, margins and derates.
Experience with Synopsys/Cadence PnR tools.
Experience with backend flows (e.g., LEC, PI/SI, DRC/LVS, etc.).
Understanding of DFT including Scan, MBIST and LBIST.
Understanding of performance, power and area (PPA) trade-offs.

Qualifications

Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
7 years of experience with physical design (e.g. from RTL to GDSII, including key stages like floorplanning, place and route, and timing closure).
Experience in Python, Tcl, or Perl scripting.

Skills

Experience working with external partners on Physical Design (PD) closure.
Experience in Static Timing Analysis (STA), with an understanding of how to define timing corners, margins and derates.
Experience with Synopsys/Cadence PnR tools.
Experience with backend flows (e.g., LEC, PI/SI, DRC/LVS, etc.).
Understanding of DFT including Scan, MBIST and LBIST.
Understanding of performance, power and area (PPA) trade-offs.