Senior ASIC Digital / DSP Design Engineer

Responsibilities

Experienced Digital & DSP/ASIC R&D engineer responsible for Digital architecture and DSP algorithm development, and RTL design and verification of digital and mixed signal ASICs.

Solves complex and high impact design and development problems including customer application issues of varying scope and complexity.

Uses product and customer applications knowledge to determine, define, develop and validate design concepts and methods.

May facilitate transition of semiconductor product design and enhancements to full production/delivery.

Participate in the entire spectrum of full ASIC design activities including definition, architectures, DSP design, digital logic design, IP validation, verification, and synthesis.

Integrate and interface with high performance analog measurement circuits and invent and develop DSP algorithms to minimize impairments and extend performance of analog circuits.

Participate in the verification of the full ASIC and the turn-on and debug of the ASIC in a product.

Qualifications

• Basic Qualifications: BS/MS in Electrical Engineering or Computer Engineering 10+ years’ experience
• Experience in the direct design and verification of digital and mixed signal ASICs and DSP algorithms either in ASICs or FPGAs
• Strong EE fundamentals with experience in ASIC Design, DSP, digital architectures/systems, and verification of large and mixed signal ASIC designs
• Solid mathematical background and fluent with Digital Signal Processing theory and Digital Design Techniques
• Proficiency in software models and how these models are used in the design, verification, and programming of an ASIC
• Leadership skills to gain credibility and respect to drive change and influence teams and partners towards higher levels of execution, return, and productivity
• Strong teamwork and written/verbal communication skills

Wanted Qualifications

• Experience with digital ASIC design methods and tools like Cadence or Mentor
• Understanding of analog design basics
• Fluent with object-oriented programming
• Experience with ASIC/FPGA design flow, methodologies, and process
• Able to multi-task and to engage with multiple projects, engineers, and partnerships
• Familiarity with test plan design, regression testing, and functional coverage

Pay

MIN $141,750.00 - MAX $236,250.00