RTL Intern

About the role

We are seeking talented interns to join our team as RTL Interns. You will be involved in designing microarchitecture and implementing logic in Verilog, contributing to the development of RTL blocks, and participating in the entire design cycle from microarchitecture discussions to synthesis and timing feedback.

Responsibilities

• Help design microarchitecture and implement logic in Verilog
• Contribute to RTL block development
• Participate in the full design cycle—from microarchitecture discussions to synthesis and timing feedback

Requirements

• Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field
• Familiarity with high-speed digital logic
• Exposure to ASIC or SoC design concepts
• Familiarity with SystemVerilog, UVM, or Python
• Familiarity with verification work and writing test benches
• Familiarity with physical design flows and tooling

Qualifications

• Able to learn quickly about transformers and other aspects of modern artificial intelligence

Skills

• Strong candidates may also have experience with modern ML and LLM model architectures
• Familiarity with numerical representations and functions
• Familiarity with clocking and reset schemes
• Ability to program with Python or another scripting language

Benefits

• 12-week paid internship
• Generous housing support for those relocating
• Daily lunch and dinner in our office
• Based at our office in San Jose (Santana Row)
• CADirect mentorship from industry leaders and world-class engineers
• Opportunity to work on one of the most important problems of our time

Pay

Details TBA

Schedule

Details TBA

Program details

12-week paid internship
Generous housing support for those relocating
Daily lunch and dinner in our office
Based at our office in San Jose (Santana Row)
CADirect mentorship from industry leaders and world-class engineers
Opportunity to work on one of the most important problems of our time

How We’re Different

We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors. We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.