RTL Design and Architect lead

Key Responsibilities

• Specification creation
• Micro-architecture development
• RTL coding
• Customer support
• Block level design
• Simulations
• Optimization
• Work with Design Verification team
• Work with Physical Design team
• Take the product from RTL to GDSII

Requirements

• Prior experience on control loops
• Micro-controller integration
• High speed peripherals
• Chiplet interconnect

Qualifications

• Bachelor’s/Master’s degree in Electronics /Electrical Engineering
• 10+ years of Industry experience
• Experience in leading SOC project
• Experienced in RTL design using VHDL/ Verilog/ System Verilog
• Strong Basics of Digital design
• Exposure to micro-processor integration is an added advantage
• Experience of working with high-speed peripheral design(DDR/PCIe/UCIe/Ethernet)
• Good communication skills and a positive working attitude
• Inclination for automation is an added advantage (Exposure to Python)