RTL Design Engineer

Responsibilities

• Developing specifications, micro-architecture, and RTL design of mission critical blocks in collaboration with the chip architect
• Integration of industry standard and Teradyne custom IPs
• Collaborating with the verification team on test plans, debug support and coverage closure to ensure high quality RTL and first pass silicon success
• Providing timing constraints and STA support to the Physical Design team through timing closure
• Providing post silicon lab bringup and debug support

Requirements

• BSEE or MSEE in Electrical Engineering or related field with 5+ years of experience.
• Extensive logic design experience writing RTL in Verilog
• Design of state machines, FIFOs, high speed data paths and arbitration logic and DFT
• Experience with logic synthesis and timing constraints
• Experience with clock domain crossings (CDC) and static timing analysis (STA)
• Experience with high speed memory and serial
• Experience with automation through scripting such as Python, Tcl & Make

Qualifications

• Strong problem-solving skills
• Excellent communication and teamwork abilities
• Ability to work independently and as part of a team
• Knowledge of mixed-signal design principles

Skills

• Verilog RTL Design
• Logic Synthesis and Timing Constraints
• High Speed Data Paths and Arbitration Logic
• Memory and Serial Interfaces
• Scripting Languages (Python, Tcl, Make)

Benefits

• Medical
• Dental
• Vision
• Flexible Spending Accounts
• Retail Savings Plans
• Life and Disability Insurance
• Paid Vacation & Holidays
• Tuition Assistance Programs

Pay

The base salary range for this role is $123,100 - $196,900. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Schedule

Full-time