Lead RTL Design Engineer

Key Responsibilities

• Own the design and definition of processor and compute-unit microarchitecture, including dataflow pipelines, execution units, and interfaces.
• Set performance, power, and area targets, and guide the team toward achieving them.
• Define and drive the design of on-chip networks and data movement across the fabric, balancing performance, scalability, and implementation constraints in collaboration with physical design.
• Define the interface to the memory subsystem, including data movement, ordering, and synchronization behavior, ensuring a clean and scalable model for software and future system expansion.
• Lead the architecture of configuration, scheduling, and execution of workloads on the fabric, including multi-kernel support and interaction with host systems.
• Drive power architecture across the design, including clocking, reset, power domains, and low-power strategies to meet aggressive energy and efficiency goals.
• Collaborate closely with compiler and software teams to define the hardware execution model, ensuring efficient mapping of workloads onto the architecture.

Specifications, Documentations and Reviews

• Author and own uArch specification documents for assigned blocks;
• Drive design reviews with architecture, compiler, DV, and physical design stakeholders.

Mentoring and Process Improvement

• Mentor senior and junior RTL engineers;
• Review RTL, flag microarchitecture risks, and enforce coding style and lint-clean standards across the team.

Driving PPA Metrics

• Participate in PPA analysis loops: synthesize blocks regularly, review area/timing/power reports, and make data-driven tradeoffs against performance and feature requirements.

DV Collaboration

• Collaborate with DV leads to define/review verification plans;
• Provide directed test scenarios for graph execution corner cases, back-pressure conditions, and power state transitions.

Silicon Bring-up

• Support silicon bring-up: contribute scan/ATPG guidelines, review DFT insertion, and provide RTL-level debug assistance during lab validation.

Required Qualifications & Experience

• 8+ years of RTL design experience with tape-out ownership of dataflow based design, on chip networks, memory subsystems or peripheral integration on a processor or accelerator.
• Deep proficiency in SystemVerilog for RTL — synthesis-clean, lint-clean, timing-aware; able to design complex state machines, arbiters, token flow controllers, and datapath logic from scratch.
• Solid understanding of parallel execution models: dataflow, SIMD, or systolic array architectures; familiarity with the hardware challenges of token-based firing-rule evaluation and producer-consumer synchronization.
• Hands-on experience with on-chip memory design: SRAM wrappers, scratchpad/TCM, banking, and memory-mapped register interfaces.
• Experience with low-power RTL techniques: UPF-driven flows, clock gating, power domains, retention registers, and AON wakeup logic.
• Familiarity with at least one standard on-chip bus protocol (AXI, AHB, APB, TileLink, or NoC equivalent) at the RTL implementation level.
• Experience taking RTL through synthesis and timing closure; ability to read and act on SDC constraints, STA reports, and synthesis QoR summaries.
• Strong written communication skills; able to produce uArch specs and design review material independently.
• Experience with memory compiler toolchains.

Desired Qualifications & Experience

• Prior RTL ownership of a dataflow engine, neural processing unit (NPU), or streaming DSP architecture with explicit producer-consumer token management.
• Experience collaborating with compiler or graph-optimization teams to co-design hardware execution models and graph IR representations.
• Familiarity with NVM controller RTL (MRAM, RRAM) including ECC, program/erase sequencing, and model weight storage use cases.
• Experience with IoT-class power budgets (sub-10 mW active, sub-100 µW standby) and the RTL design choices they necessitate.
• Familiarity with functional safety standards (ISO 26262, IEC 61508) as applied to execution fabric error detection and power domain isolation.
• Exposure to AI framework graph formats (ONNX, TFLite) and understanding of how graph compilation maps to hardware execution primitives.
• Tape-out credits on an edge-AI, IoT, or wearable SoC at 12nm or below.
• Experience with formal verification of flow-control logic, deadlock freedom, or bus protocol compliance.