R&D Engineer IC Design

About the role

Engineer will be responsible for verification of complex switch designs, including creating SystemVerilog-based verification environments, testplans, and executing verification at both the block and chip level. The role also involves creating ATE testing vectors and C-based diagnostic tests for actual silicon.

Responsibilities

• Create SystemVerilog-based verification environments (testbenches, checkers, transactors).
• Develop and execute testplans for verification of RTL and gatesim-based designs at block and chip levels.
• Generate ATE testing vectors.
• Develop C-based diagnostic tests to run on actual silicon.

Requirements

• Master's Degree in Electrical and Electronic Engineering, Computer Science, or equivalent.
• Minimum of 6 years of work experience in Design Verification.
• Strong knowledge and hands-on experience in verification methods, tools, and environments.
• Proficiency in SystemVerilog and scripting languages.

Qualifications

• Knowledge and experience in UVM methodology is preferable.
• Knowledge of networking and switching concepts is a plus.

Pay

Annual base salary range: $120,000 – $192,000.

Benefits

• Discretionary annual bonus.
• Equity in accordance with company plans.
• Medical, dental, and vision plans.
• 401(K) participation with company matching.
• Employee Stock Purchase Program (ESPP).
• Employee Assistance Program (EAP).
• Paid holidays, sick leave, and vacation time.
• Paid Family Leave and other leaves of absence in compliance with applicable laws.