R&D Engineer IC Design 4

About the role

You will be responsible for the front-end design and verification of design blocks for cores. You will work independently as well as part of a large team spanning multiple geographies.

Responsibilities

• Architecture definition, logic design, synthesis, and constraint development
• Design verification through simulation, formal verification, and timing analysis from physical implementation
• Design logic blocks from systems requirements documents
• Simulate and debug designs with Verilog simulation
• Work within the complete ASIC design and implementation flow

Requirements

• BS/MS in Electrical or Computer Engineering or equivalent
• 8+ years of related experience with a Bachelor’s degree, or 6+ years with a Master’s degree
• Experience with complete ASIC or standard product implementation flow from RTL synthesis and timing analysis/closure

Skills

• Proficiency with TCL/Perl scripting
• Synthesis experience with Synopsys Design Compiler/DC Topo or Cadence RTL Compiler
• Timing analysis experience with Primetime for high-frequency designs and advanced technology nodes/libraries
• Understanding of liberty LIB models for timing
• Formal verification (Synopsys Formality/Cadence Conformal)
• Spyglass Lint
• Power analysis of RTL and gate-level netlists
• Familiarity with DFT (Design for Test) and scan methodology
• Version control (SVN, Git, etc.)

Pay

The annual base salary range for this position is USD 121,900 to USD 195,000.

Benefits

• Discretionary annual bonus
• Competitive new hire equity grant and annual equity awards
• Medical, dental, and vision plans
• 401(K) participation with company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Paid holidays, sick leave, and vacation time
• Paid Family Leave and other leaves of absence as per applicable laws