R&D Engineer IC Design

About the role

Engineer will be responsible for verification of complex switch designs.

Responsibilities

• Creating SystemVerilog-based verification environments (testbenches, checkers, transactors)
• Creating and executing testplans for verifications of RTL and gatesim-based designs at both the block and chip level
• Creating ATE testing vectors, as well as C-based diagnostic tests to be run on the actual silicon

Requirements

• Master's Degree in Electrical and Electronic Engineering, Computer Science, or equivalent
• Minimum of 3 years of work experience in Design Verification
• Strong knowledge and hands-on experience in verification methods, tools and environment
• Strong programming skills, including in System Verilog and scripts languages

Qualifications

• Knowledge and experience in UVM methodology is preferable
• Knowledge of networking and switching concept is a plus

Pay

USD 121,900.00 To USD 195,000.00 annual base salary range. Eligible for a discretionary annual bonus and competitive new hire equity grant plus annual equity awards.

Benefits

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company paid holidays, paid sick leave and vacation time
• Paid Family Leave and other leaves of absence as applicable by law