Process integration and Defect Reduction Engineer

About the Role

The New Mexico Silicon Manufacturing (NM Si Mfg) Yield Department is seeking Process Integration and Defect Reduction Engineers to support backend interconnect and advanced packaging semiconductor fabrication. These roles support Fab 11X, with a focus on Intel's Foveros and EMIB technologies. You will partner with teams across Yield Engineering, including Process Integration, Defect Reduction, Quality and Reliability, Device Analysis, and Yield Analysis. The role involves sustaining process health as products transition from development into high-volume manufacturing (HVM) while driving improvements in yield, quality, reliability, cost, and manufacturability.

Responsibilities

• Design and execute experiments, analyze process and yield data, and optimize manufacturing processes to reduce defects and improve overall product performance.
• Manage technology change introductions and monitor inline defectivity and parametric performance.
• Investigate process excursions, identify root causes, and implement corrective actions.
• Support the transfer of new products from Technology Development (TD) into manufacturing and ensure readiness for successful high-volume production.

Desired Skills and Behavioral Traits

• Strong teamwork, leadership, problem-solving, and prioritization skills in a high-performance environment.
• Excellent written and verbal communication skills, with the ability to present technical information clearly to audiences with varying levels of expertise.
• Ability to work independently with minimal supervision while managing multiple priorities.
• Experience leading factory-level projects and delivering results in a timely manner.
• Strong project management skills, with the ability to execute roadmaps that drive improvements in yield, defect reduction, efficiency, and cost.
• Ability to balance collaboration and critical thinking to drive data-based decisions and technical solutions.

Qualifications

Minimum Qualifications

• Bachelor's or Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, Materials Science, Microelectronics Engineering, Chemistry, Physics, or a related technical field.
• 3+ years of experience in the semiconductor industry.

This position is not eligible for Intel immigration sponsorship.

Preferred Qualifications

• 3+ years of experience in process integration or defect reduction for backend interconnect or advanced packaging processes.
• 3+ years of experience applying Design of Experiments (DOE) methodologies.
• 3+ years of experience in data analysis and statistical process control using tools such as JMP, SQL, PCS, or similar platforms.
• Strong understanding of semiconductor manufacturing process flow and advanced packaging technologies.
• Knowledge of process capability, specification limits, statistical variation, and process control methodologies.

Pay

Annual Salary Range for jobs which could be performed in the US: $120,860.00 - $170,630.00 USD. The range reflects the minimum and maximum target compensation for the position across all US locations. Individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.

Schedule

This role requires an on-site presence on Shift 1 (United States of America).

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.