Principal Physical Design/Implementation Engineer

About the role

This position is for either our Santa Clara or Irvine locations. Being on site full-time is required. Relocation will be provided.

Responsibilities

• Architect and lead the development of next-generation physical design methodologies and automation flows for Complex SubSystems
• Provide deep technical leadership in RTL-to-GDSII implementation, including synthesis, floor planning, place and route, clock tree synthesis, and timing closure
• Hands-on work on complex Subsystem hardening
• Work with Senior and Junior engineers to deliver reference floorplan, fully synthesized, timing-closed Sub System partitions to SOC team
• Work with DFT team and SOC team for DFT insertion and closing timing at SOC level
• Work with RTL team to close timing, ECOs, bug fixes, etc.
• Serve as a key technical advisor across multiple projects, influencing design decisions and resolving complex implementation challenges
• Collaborate with global cross-functional teams, including RTL, verification, and CAD, to ensure cohesive and optimized design execution
• Mentor and coach senior and junior engineers, fostering technical growth and promoting best practices across the organization
• Evaluate and drive adoption of emerging EDA tools and technologies in partnership with internal CAD and external vendors
• Represent the physical design team in strategic technical discussions with internal and external stakeholders, contributing to roadmap planning and methodology evolution

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience or equivalent professional experience in lieu of a formal degree
• Domain expertise of SoC architecture, processor cores, memory, PCIE/CXL highly preferred
• Ethernet, Security and peripheral interfaces through hands-on prior experience preferred
• Experience with large and complex design synthesis, floor planning, place and route, clock tree and timing closure of large Subsystems
• Extensive experience in Verilog and Static Quality checks of the implemented RTL
• Experience with Memory generation highly preferred
• Experience with leading foundries and latest process nodes (2nm, 3nm, 5nm, etc.) preferred
• Hands-on experience in interpretive language such as Perl/Python
• Proven track record of delivering production-quality designs on aggressive development schedules
• Good communication skills and self-discipline contributing in a team environment

Pay

Expected Base Pay Range (USD): $154,680 - $231,700 per annum. The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location, and market conditions.

Benefits

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage—from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include:

• Employee stock purchase plan with a 2-year look back
• Family support programs to help balance work and home life
• Robust mental health resources to prioritize emotional well-being
• Recognition and service awards to celebrate contributions and milestones