Principal Engineer, Physical Design

Responsibilities

• Complete entire physical implementation of the block and chip level
• Perform synthesis and physical implementation steps – synthesis, floor-planning, power delivery, place&route, timing noise, physical verification, IR/RV.
• Collaborate with the SOC design team to drive architectural feasibility studies, develop timing, power, and area design targets, and explore RTL/design tradeoffs
• Analyze the quality of the floorplan and Customized Clock tree structure and Place & Route
• Implement ECOs for timing closure
• Signal EM/Noise and Power IR/EM analysis and fix
• DRC/LVS/ERC/ANTENNA analysis and clean up
• Timing verification and signoff
• Physical verification and signoff

Minimum Qualifications

• Master’s degree or above in electrical/computer science engineering with 10+ years of industry experience, or bachelor’s degree in electrical/computer science engineering plus 15+ years of industry experience
• Strong experience in Power/Ground grids, Partitioning, Timing ECO implementation, and physical verification.
• The entire SOC implementation and verification flow from RTL-to-GDS that includes fullchip floorplan, place and route, CTS, and layout verification signoff on lower power SoC
• Netlist (or RTL)-GDS physical implementation experience
• In depth knowledge of major EDA tools/design flows
• Strong Cadence experience/background
• Experience with TSMC N22 or below technology
• Experience in chip integration and signoff
• Experience in Perl/TCL language programming

Preferred Qualifications

• Strong experience in Low-power implementation methodology
• Strong experience in Advanced timing signoff methodology
• Knowledge of DFT (BSCAN, MBIST, SCAN) and understanding of their impact on physical design flows
• Able to independently complete Netlist-GDS P&R, signoff task
• Proven record in multi-million gate design production tapeouts