PRINCIPAL PCIE LOGIC DESIGN

Rambus, a premier chip and silicon IP provider, is seeking a motivated full-time Principal Design Engineer to join our PCIe IP design team. Candidates will collaborate with some of the brightest inventors and engineers globally to develop products that accelerate and secure data.

About the role

This position focuses on the architecture and design of next-generation IPs, targeting the latest advancements in PCIe standards. The role also involves prototyping these IPs on cutting-edge FPGAs. You will work closely with local teams and multi-cultural, multi-national colleagues.

Responsibilities

• Contribute to the architecture and design of next-generation PCIe IP solutions.
• Prototype IPs on advanced FPGAs to validate and refine designs.
• Collaborate with cross-functional teams, including local and international colleagues.

Requirements

• Proven experience in digital design and IP development, particularly in PCIe or related high-speed interfaces.
• Strong background in FPGA prototyping and validation.
• Ability to work effectively in a global, multi-cultural team environment.