Principal ASIC Verification Engineer

This role is hybrid, requiring an average of 2 days per week in an HPE office.

About Us

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live—from edge to cloud—so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We value varied backgrounds and succeed here by embracing flexibility, innovation, and teamwork. If you are looking to stretch and grow your career, our culture will embrace you.

About the Role

HPE Networking is a leading provider of advanced routers and switches for the internet, ensuring speed, reliability, security, and ease of use. Within the HPE Networking Silicon group, we push the boundaries of silicon technology to build cutting-edge networking chips used in our world-class routers and switches. This is a hybrid role based in Sunnyvale, CA, offering a start-up-like environment within a large company. You will work on complex modules and subsystems, challenging yourself and growing as an expert in high-speed ASIC development.

Responsibilities

• Own and drive block-level or subsystem verification efforts, from creating test plans to achieving comprehensive coverage closure.
• Develop, enhance, and maintain advanced UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models.
• Perform constraint-driven random testing, debug complex SoC designs, and ensure functional coverage and assertion goals are met.
• Analyze simulation results using industry-leading simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and debug waveforms to validate design functionality.
• Collaborate with cross-functional teams to identify and resolve issues, ensuring high-quality ASIC/SoC deliverables.

Requirements

• 15+ years of experience in ASIC/SoC verification with a proven track record of owning verification from test plan to coverage closure.
• Strong expertise in SystemVerilog and UVM methodology, including developing environments from scratch.
• Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
• Hands-on experience in test planning, coverage analysis, and debugging of complex SoC designs.
• Proficiency with industry-standard simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and waveform debugging.

Preferred Qualifications

• Experience verifying networking ASICs or router datapath/control blocks, such as packet processing, forwarding engines, or fabric interfaces.
• Familiarity with high-speed interconnects, buffers, or scheduling pipelines in large networking SoCs.
• Exposure to emulation environments, hardware acceleration, or traffic-model integration.
• Knowledge of coverage analytics, regression dashboards, and continuous-integration flows (e.g., Jenkins).
• Understanding of low-power (UPF) or formal verification methodologies.
• Experience with post-silicon bring-up and debug.
• Familiarity with emulation environments and debug flows.

Benefits

• Health & Wellbeing: Comprehensive suite of benefits supporting physical, financial, and emotional wellbeing for you and your loved ones.
• Personal & Professional Development: Programs to help you reach career goals, whether becoming a knowledge expert or applying skills to another division.
• Unconditional Inclusion: Celebration of individual uniqueness with flexibility to manage work and personal needs.

Pay

The expected salary range for this position in California is USD 174,000 - 352,500 annually (base salary). Variable incentives may also be offered.