Principal ASIC Verification Engineer

Key Technical Responsibilities

• Define overall SOC level verification strategy, technical planning, direction
• Enable and drive the development of UVM environments to verify RTL at block, unit, and SoC levels
• Develop and execute functional tests according to verification test plans
• Instrument TB for functional and code coverage and drive to closure based on the coverage metrics
• Collaborate with cross-functional teams like design, software, emulation and silicon validation teams towards ensuring the highest design quality

Team Responsibilities

• Day-to-day guidance and leadership of team members
• Driving results via mentoring, coaching, and counseling
• Education of team in the use of AI tools to enhance productivity and efficiencies
• Generation and enforcement of coding and verification guidelines

Minimum Qualifications

• 15 + years of experience with the following:
• Hands-on experience with writing code using UVM/System Verilog
• Verification for complex SoCs that include multiple clock and reset domains, using VCS or equivalent simulation tools
• Debugging fails to the line of RTL, closing out bug fixes, using Verdi or equivalent debug tools
• Experience in ground up testbench development
• Experience with revision control systems like Git or SVN etc.
• B.S. Degree in Computer Engineering, Computer Science, or Electrical Engineering

Preferred Qualifications

• M.S. Degree in Computer Engineering, Computer Science, or Electrical Engineering
• 15 + years of relevant experience in networking hardware verification, proven expertise in verifying 50G, 100G, 400G Ethernet MAC/PCS protocols, TCP/IP, RDMA/RoCE, IPSec. and their application in high-speed data processing/networking
• Experience with one or more scripting languages (TCL, Python, Perl, Shell-scripting)
• Track record of first-pass success in ASIC and Systems