Photonic Integrated Circuit Fabrication

MIT Lincoln Laboratory’s RF and Integrated Photonics Group (Group 85) advances technologies in the national interest by developing novel RF and photonic capabilities, from foundational materials research to complete systems. Key application areas include classical and quantum sensing and computing, laser and radar systems, communications, and electronic warfare. The integrated photonics team focuses on photonic integrated circuits (PICs) and active photonic devices for microwave photonics, ion-trap quantum computing, quantum sensing and communication, advanced laser and modulator development, and nonlinear photonic applications. These efforts leverage state-of-the-art on-site fabrication tools, university and industry partnerships, and extensive test and measurement infrastructure.

About the role

The group seeks a highly motivated scientist or engineer to join the integrated photonics fabrication team. The successful candidate will play a central role in developing PIC fabrication processes for monolithic and hybrid-integrated circuits for both classical and quantum applications, primarily using 200 mm PIC fabrication platforms in the in-house Microelectronics Laboratory. Responsibilities include initiating and executing short-loop and full-flow fabrication runs, overseeing standard process runs, monitoring in-line process metrology, and performing process integration. The role involves hands-on process activities in compound semiconductor and auxiliary fabrication spaces, working collaboratively with engineers and scientists across various skill levels.

Responsibilities

• Develop and execute PIC fabrication processes for monolithic and hybrid-integrated circuits.
• Initiate and oversee short-loop and full-flow fabrication runs in the 200 mm Microelectronics Laboratory.
• Monitor in-line process metrology and perform process integration.
• Support fabrication runs, improve device performance, yield, and reliability.
• Process experiments and complete independent tasks while collaborating with a multidisciplinary team.
• Leverage standard back-end-of-line CMOS techniques, including metal deposition, photolithography, and etch.

Requirements

• Ph.D. or M.S. in a field related to nanofabrication with at least 3 years of hands-on experience in micro/nanofabrication process engineering or process integration. Exemplary candidates with a B.S. and extensive fabrication expertise will also be considered.
• Demonstrated ability to develop and execute rigorous experimental plans.
• Tool operation expertise and theoretical understanding in at least one of the following: lithography, etch, thin films, metrology, or inspection.

Qualifications

• Tool operation expertise and theoretical understanding across multiple areas: lithography, etch, thin films, metrology, and inspection.
• Demonstrated skill in Scanning Electron Microscopy (SEM).
• Experience with full device fabrication flows and standard process control.
• Process integration and 3D integration experience.
• Prior experience in hybrid or heterogeneous multi-material integration (e.g., chemical mechanical polishing, surface preparation, chip-to-wafer or wafer-to-wafer bonding) is a plus.
• Experience with novel material etch development and qualification is advantageous.

Pay

• Recent Graduate Hiring Range: $145,200–$170,000
• Experienced Hiring Range: $145,200–$220,000

Final salary will depend on experience, skills, education, internal equity, and applicable legal requirements. This range reflects base salary only.

Benefits

• Comprehensive health, dental, and vision plans.
• MIT-funded pension and matching 401K.
• Paid leave (vacation, sick, parental, military, etc.).
• Tuition reimbursement and continuing education programs.
• Mentorship programs and work-life balance options.
• Additional voluntary benefits, discounts, and perks through MIT.

Selected candidate will be subject to a pre-employment background investigation and must obtain and maintain a Secret-level DoD security clearance.