Memory System Designer and Place and Route Engineer

Job Description: We are looking for an energetic and passionate design engineer to join our Central Engineering Group and be part of a memory subsystem design team responsible for the development of large memory blocks and subsystems. Typically requires a minimum of 8 years of relevant experience and a Bachelor in Electrical Engineering. Job Responsibilities Architect and design memory subsystemsImplement RTL of subsystem designsPlace and route (physical design) Design closure: timing, DRC, LVS, EM/IR, etc.Gate netlist synthesis Skill Set Required Strong design skillsAbility to write and debug Verilog RTL codePlace and route expertiseProficient in running STA, DRC, EM/IR tools, and attaining design closureAbility to code in PythonGood understanding of synthesis tools and running synthesisCapable of running and debugging logical equivalency checkersFamiliar with memory behaviorProficient in writing automation scripts, and tools savvyGood communication, interpersonal, and leadership skillsMotivated, self-driven, and good at multitasking Compensation And Benefits The annual base salary range for this position is USD 109,700.00 To USD 175,500.00 As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. R027233