Memory System Designer and Place and Route Engineer

About the role

We are looking for an energetic and passionate design engineer to join our Central Engineering Group and be part of a memory subsystem design team responsible for the development of large memory blocks and subsystems.

Responsibilities

• Architect and design memory subsystems
• Implement RTL of subsystem designs
• Place and route (physical design)
• Design closure: timing, DRC, LVS, EM/IR, etc.
• Gate netlist synthesis

Requirements

Typically requires a minimum of 8 years of relevant experience and a Bachelor in Electrical Engineering.

Skills

• Strong design skills
• Ability to write and debug Verilog RTL code
• Place and route expertise
• Proficient in running STA, DRC, EM/IR tools, and attaining design closure
• Ability to code in Python
• Good understanding of synthesis tools and running synthesis
• Capable of running and debugging logical equivalency checkers
• Familiar with memory behavior
• Proficient in writing automation scripts, and tools savvy
• Good communication, interpersonal, and leadership skills
• Motivated, self-driven, and good at multitasking

Pay

The annual base salary range for this position is USD 109,700.00 To USD 175,500.00 As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Benefits

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company paid holidays
• Paid sick leave and vacation time
• The company follows all applicable laws for Paid Family Leave and other leaves of absence