Hardware Design Engineer IV

About the Role

As a member of the CT Server DDR team, we are looking for an experienced signal integrity and power integrity engineer who will be responsible for DDR PHY channel and power delivery network (PDN) architecture, system-level SI/PI, and post-silicon validation. The engineer will define channel and PDN architectures, model signal and power delivery at the system level, and validate SI/PI on silicon. The role involves collaboration with design, package, board, and firmware teams to specify SI/PI targets, implement solutions, and debug issues across the full system stack.

Responsibilities

• Run system-level channel and PDN simulations (insertion/return loss, crosstalk, eye diagrams, impedance, IR drop, jitter transfer) and correlate with silicon results.
• Process post-silicon SI/PI validation data and drive next steps.
• Debug SI/PI issues across silicon, package, and board, working with firmware and design teams.
• Support cross-functional teams with system, channel, PDN, and decoupling implementation details.

Requirements

• Strong coding skills in Python and Matlab (preferred).
• Signal integrity (SI) and power integrity (PI) knowledge, including S-parameter/Z-parameter analysis, channel modeling, and PDN modeling.
• Experience with Ansys or Cadence simulation tools (e.g., HFSS, SIwave, Sigrity, Clarity).
• System-level experience with firmware and hardware debug (preferred).
• System modeling with silicon-to-simulation correlation.
• Firmware development for ATE and platforms (preferred).

Qualifications

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.

Pay

$60.00/hour.

Schedule

• Duration: 12 months.
• Work Type: Onsite (San Jose, CA).
• Job Type: Temporary Assignment.