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Full-Chip Physical Design Verification Engineer

Tenstorrent · Santa Clara, CA · 6 days ago
RemoteRemoteEngineering$100k–$500k/yrFull-time

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems.

About the role

Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. You’ll lead physical verification closure (DRC, LVS, ERC, etc.), debug issues using standard industry PV tools, and collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts. This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role.

Responsibilities

  • Lead physical verification closure (DRC, LVS, ERC, etc.) for full-chip signoff.
  • Debug issues using industry-standard physical verification tools.
  • Collaborate with RTL, PD, CAD, and packaging teams to ensure successful tapeouts.
  • Mentor and provide technical leadership in building efficient, manufacturable silicon.

Requirements

  • BS/MS in Electrical/Electronics Engineering (or related) with 7–14 years of hands-on CPU/IP/SoC physical verification experience.
  • Proven expertise in DRC, LVS, ERC, PERC, Antenna, and DFM verification using industry-standard tools (Calibre, ICV, Pegasus, FC, Innovus, etc.).
  • Strong background in ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop, EM).
  • Solid understanding of advanced nodes (7nm, 5nm, 3nm) and FinFET design challenges.
  • Scripting proficiency in Python and TCL for automation and flow optimization.

Skills

  • Hands-on problem solver with a strong background in CPU/IP/SoC physical verification and tapeout closure.
  • Collaborative team player who works effectively across RTL, PD, CAD, and foundry interfaces.
  • Passionate about building efficient, manufacturable silicon and mentoring others.

What You Will Learn

  • Advanced physical verification methodologies and flow optimization for next-generation SoCs.
  • Integration and verification strategies for full-chip signoff across advanced process technologies.
  • Cross-functional collaboration across design, CAD, and foundry teams to ensure flawless tapeouts.
  • Leadership and mentoring opportunities in building scalable PV methodologies and automation.

Pay

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background, and location all impact the actual offer made.

Additional Information

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. The offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.

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