Chip Design and Verification Methodology Engineer

About the role

TenX Semi is reinventing how chips are designed to provide a seismic shift in the industry. The Chip Design and Verification Methodology Engineer will develop innovative methodologies to ensure the functional correctness of AI-generated RTL, architecting a verification loop that maximizes automation and identifies critical bugs.

The company was founded by a Stanford University professor (Prof. Subhasish Mitra) and former Samsung EVP Suk Hwan Lim, and has a world-class team from Google, Meta, Apple, Broadcom, Stanford, Synopsys, with eight-figure backing raised from top-tier VCs.

Why Join Us

• Build and improve AI that is redefining how next-generation chips are designed and verified while leveraging self-verifying-and-fixing loop using AI and formal methods.
• Work at the intersection of AI, formal verification, and chip design, one of the most technically challenging but rewarding problems in engineering.
• Join an early team with the opportunity to shape both the product and the future of AI-native chip design.

Role Responsibilities

• Drive Verification Methodology and Environment: Take responsibility for the full verification lifecycle of AI-generated design with maximal automation.
• Architect Test Environments: Write clean, modular, and reusable verification environments/harnesses that can scale across customer designs.
• Build Convergence Monitoring: Develop systems that track verification progress, measure coverage, and provide guarantees about design correctness.
• Deep-Dive Debugging: Go beyond pass/fail logs, build advanced tools to read, parse, and analyze waveforms, tracing signal dependencies to pinpoint the root cause of logic failure.
• Collaborate on AI Integration: Work closely with AI engineers to ensure verification feedback improves model accuracy.
• Formal Proof Generation: Develop formal proofs for critical design paths, ensuring that safety-critical properties hold under all conditions.

Qualifications

• Verilog and SystemVerilog Fluency: Expert-level proficiency in writing Verilog and SystemVerilog.
• SystemVerilog Assertions: Strong experience writing SystemVerilog Assertions.
• UVM Expertise: Deep experience with UVM methodology, including constrained-random verification, functional coverage, and scoreboards.
• Computer Architecture Fundamentals: Solid understanding of Computer Architecture and Digital Design fundamentals.
• Waveform Analysis: Proven ability to read and analyze simulation waveforms to resolve complex logic issues.
• Automation Mindset: Strong Python/scripting skills and a passion for automating everything that can be automated.

Preferred Qualifications

• Hands-on experience with commercial formal tools such as JasperGold or VC Formal.
• Deep knowledge of standard on-chip interface protocols like AXI, AHB, APB, CHI, PCIe, or CXL.
• Experience at EDA vendors or leading semiconductor companies.
• Familiarity with AI/ML concepts and interest in how AI can transform chip design.
• MS or PhD in Electrical Engineering or Computer Science.

Pay

The salary for this role is $150K/yr - $300K/yr.