Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

About the role

SpaceX is actively developing the technologies to make a future where humanity is out exploring the stars possible, with the ultimate goal of enabling human life on Mars. We are seeking a motivated, proactive, and intellectually curious engineer to work alongside world-class cross-disciplinary teams to develop cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe.

Responsibilities

• Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools like Calibre, ICV, or Pegasus
• Develop, maintain, and optimize physical verification flows for advanced node SoC’s
• Interpret and implement foundry Design Rule Manuals (DRM) — translate rule updates into verified flow changes
• Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs
• Perform ESD verification — validate protection strategies, current paths, and CDM/HBM compliance
• Drive tapeout readiness by coordinating signoff across block and top-level and Hard IP design teams
• Engage directly with foundry teams to resolve DRM ambiguities and waiver requests
• Develop/modify design flows as needed to meet the overall design quality of results and chip integration requirements
• Leverage AI agents to automate rule deck validation, violation triage, and signoff reporting workflows

Qualifications

Bachelor’s degree in electrical engineering, computer engineering or computer science and 5+ years of ASIC and/or physical design flow development experience in industry.

Skills

• Experience and deep understanding of SOC top level physical design flows (floor-planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, special interface/interconnect planning and implementation)
• Experience in IP integration (e.g. memories, I/O’s, analog IPs, SerDes, DDR etc.)
• Deep expertise in DRC, LVS, PERC and ESD verification methodologies
• Hands-on proficiency with Calibre, ICV (IC Validator), or Pegasus
• Direct foundry DRM experience — able to read, interpret, and implement complex rule decks
• Experience at advanced nodes (4nm and below)
• Experience with large SOC designs (>10M gates) with frequencies in excess of 1GHZ
• Excellent scripting skills (csh/bash, Perl, Python TCL, Makefile etc.)
• Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment

Additional Requirements

Ability to work extended hours and weekends as needed to meet critical project milestones. To conform to U.S. Government export regulations, applicant must be a U.S. citizen or national, U.S. lawful permanent resident, Refugee under 8 U.S.C.1157, or Asylee under 8 U.S.C.1158, or be eligible to obtain the required authorizations from the U.S. Department of State.