CPU Design Methodology Engineer
About the Role
The complexity of chip development has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The NVIDIA CPU team is looking for a top ASIC Engineer with an interest in SOC design automation, RTL integration, and chip build and assembly. You should be passionate about developing methodologies and automation solutions that enable SOC creation in the most optimized way. In this position, you will get the chance to build complex chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT, and other teams.
Responsibilities
- Define and develop system-level methodologies and tools to build SOCs in an efficient and scalable manner
- Identify inefficiencies and improvement opportunities in the front-end chip implementation process and propose ideas to address them
- Own front-end design quality checks and reviews to present the physical design team with high-quality RTL
Requirements
- 8+ years of experience in chip design, specializing in SOC integration and design automation
- Experience in RTL design (Verilog), verification (UVM, System Verilog), System-On-Chip design/integration flow, and design automation liStrong coding skills in Perl, Python, or other industry-standard scripting languages
Qualifications
- A Masters in Computer or Electrical Engineering or equivalent experience
- Experience in synthesis and physical design is a plus
- Good interpersonal skills
Pay
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until August 22, 2026. This posting is for an existing vacancy.