CPU Design Methodology Engineer
We are packing tens of billions of transistors in a chip to meet growing computing demand while maintaining a responsible environmental footprint. The NVIDIA CPU team is looking for a top ASIC Engineer with an interest in SOC design automation, RTL integration, and chip build and assembly.
About the role
You will develop system-level methodologies and automation solutions that enable SOC creation in the most optimized way. In this position, you will build complex chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT, and other teams.
Responsibilities
- Define and develop system-level methodologies and tools to build SOCs in an efficient and scalable manner
- Identify inefficiencies and improvement opportunities in the front-end chip implementation process and propose ideas to address them
- Own front-end design quality checks and reviews to present the physical design team with high-quality RTL
Requirements
- Master’s in Computer or Electrical Engineering or equivalent experience
- 5+ years of experience in chip design, specializing in SOC integration and design automation
- Excellent analytical and problem-solving skills
- Experience in RTL design (Verilog), verification (UVM, System Verilog), System-On-Chip design/integration flow, and design automation
- Strong coding skills in Perl, Python, or other industry-standard scripting languages
- Experience in synthesis and physical design is a plus
- Good interpersonal skills
Pay
Base salary range: 136,000 USD – 218,500 USD (Level 3) or 168,000 USD – 264,500 USD (Level 4), depending on location, experience, and position level. Eligible for equity and benefits.