CPU Design Methodology Engineer

We are packing tens of billions of transistors in a chip to meet growing computing demand while maintaining environmental responsibility. The NVIDIA CPU team seeks a top ASIC Engineer interested in SOC design automation, RTL integration, and chip build and assembly.

Responsibilities

• Define and develop system-level methodologies and tools to build SOCs in an efficient and scalable manner
• Identify inefficiencies and improvement opportunities in the front-end chip implementation process and propose ideas to address them
• Own front-end design quality checks and reviews to present the physical design team with high-quality RTL

Requirements

• Master’s in Computer or Electrical Engineering or equivalent experience
• 8+ years of experience in chip design, specializing in SOC integration and design automation
• Excellent analytical and problem-solving skills
• Experience in RTL design (Verilog), verification (UVM, System Verilog), System-On-Chip design/integration flow, and design automation
• Strong coding skills in Perl, Python, or other industry-standard scripting languages
• Experience in synthesis and physical design is a plus
• Good interpersonal skills

Pay

Base salary range: $168,000 – $264,500 USD (Level 4) or $196,000 – $310,500 USD (Level 5), plus equity and benefits.