ASIC DFT STA Technical Lead

Application window expected to close on 08/25/2026; posting may be removed earlier if the position is filled or sufficient applications are received.

About the team

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly.

About the role

You will be in the Silicon One development organization as an ASIC DFT STA Technical Lead. You are a detail-oriented STA engineer with strong analytical skills and a deep understanding of timing constraints, such as clock groups, various exceptions, and clock exclusivity. You will collaborate with cross-functional teams, communicate complex timing data clearly, and help drive the DFT and quality process through the entire implementation flow and post-silicon validation phases, with additional exposure to physical design signoff activities.

Responsibilities

• Develop timing constraints at block, sub-chip, and full-chip levels in test modes, performing quality checks such as duplicated constraints, promotion/demotion between block and top-level SDCs.
• Check timing for unconstrained endpoints, no clock, etc.
• Perform SDC validation, CDC delay check, and SDC flow development.
• Develop methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy.
• Contribute to crafting groundbreaking next-generation networking chips.

Requirements

• Bachelor’s degree + 8 years of related experience, or Master’s degree + 6 years of related experience, or PhD + 3 years of related experience.
• Prior working experience with RTL design, CDC/RDC and conformal verification, SDC development.
• Prior working experience in timing constraint development and verification.
• Prior programming experience with at least 2 or more of the following scripting languages: Perl, TCL, Python, or Makefile.

Preferred Qualifications

• Master’s degree + 15+ years of experience.
• Prior working experience in debugging and analyzing PCIe timing constraints, TSMC memory timing constraints.
• Prior working experience in debugging and analyzing timing constraints, timing closure of DFT modes such as scan shift/capture and BIST.
• Prior working experience with SDC debugging & STA tools like Synopsys TCM/PrimeTime.
• Prior working experience with synthesis tools: Synopsys Fusion/Design Compiler.
• Prior working experience with Tessent tools like DFT insertion in RTL.

Benefits

• Medical, dental, and vision insurance.
• 401(k) plan with Cisco matching contribution.
• Paid parental leave, short- and long-term disability coverage, and basic life insurance.
• Restricted stock units (RSUs) that vest following continued employment.
• Paid time off:
  • 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees.
  • 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness.
  • Non-exempt employees: 16 days of paid vacation time per full calendar year, accrued at 4.92 hours per pay period.
  • Exempt employees: Flexible vacation time off program with no defined limit (subject to business limitations).
  • 80 hours of sick time off provided on hire date and each January 1st thereafter, with up to 80 hours of unused sick time carried forward.
  • Additional paid time away for critical or emergency family issues.
  • Optional 10 paid days per full calendar year to volunteer.
• Annual bonuses for non-sales roles, subject to Cisco’s policies.
• For sales roles: Performance-based incentive pay split between quota and non-quota components, with uncapped earnings potential beyond 100% attainment.

Pay

The starting salary range for this position is $168,800.00 to $241,200.00 (U.S. and Canada locations, excluding specific states listed below). Individual pay is determined by hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and training.

• New York City Metro Area: $168,800.00 - $277,400.00
• Non-Metro New York State & Washington State: $148,800.00 - $248,200.00
• For sales roles: Ranges include base pay and sales target incentive compensation combined.