ASIC STA Technical Lead

About the role

You will be in the Silicon One development organization as an ASIC DFT STA Technical Lead. You are a detail-oriented STA engineer with strong analytical skills and a deep understanding of timing constraints, such as clock groups, various exceptions, clock exclusivity. You will collaborate with cross-functional teams, communicate complex timing data clearly. As a member of this team, you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.

Responsibilities

• Collaborate with cross-functional teams, communicating complex timing data clearly.
• Help lead the DFT and quality process through the entire implementation flow and post silicon validation phases.
• Engage in crafting groundbreaking next generation networking chips.
• Lead the DFT and quality process through the entire implementation flow and post silicon validation phases.
• Contribute to physical design signoff activities.

Requirements

• Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience
• Prior working experience with RTL design, CDC/RDC and conformal verification, SDC development
• Prior working experience in timing constraint development and verification
• Prior programming experience with at least 2 or more of the following scripting languages: Perl, TCL, Python, or Makefile

Preferred Qualifications

• Masters degree + 15+ years experience
• Prior working experience in debugging and analyzing PCIE timing constraints, TSMC memory timing constraints
• Prior working experience with RTL design, CDC/RDC and conformal verification
• Prior working experience in debugging and analyzing timing constraints, timing closure of DFT modes such as scan shift/capture and BIST
• Prior working experience with SDC debugging & STA tools like Synopsys TCM/Primetime
• Prior working experience with synthesis tools: Synopsys Fusion/design Compiler
• Prior working experience with Tessent tool like DFT insertion in RTL

Skills

Detail-oriented STA engineer with strong analytical skills and a deep understanding of timing constraints, such as clock groups, various exceptions, clock exclusivity. Prior working experience with RTL design, CDC/RDC and conformal verification, SDC development. Prior programming experience with at least 2 or more of the following scripting languages: Perl, TCL, Python, or Makefile.

Benefits

The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

• New York City Metro Area: $186,900.00 - $307,800.00
• Non-Metro New York State & Washington State: $166,300.00 - $274,100.00

Pay

The starting salary range posted for this position is $186,900.00 to $267,700.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Schedule

Not specified.