ASIC Physical Design Technical Lead

About the Team

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly.

Responsibilities

• Full-chip Floorplan by understanding the architecture of the design, foundry integration guidelines, and IP placement constraints.
• Collaborate with the system and package design teams to understand requirements and incorporate them into the full-chip floorplan.
• Perform hierarchical implementation flow, including partition, pin assignment, clock plan, and bump planning; hands-on experience with Full-chip clock mesh and Flex-HTree methods.
• RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification, and equivalence checks with a focus on performance, power, and die size optimization.
• Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements.
• Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable best-in-class design methodology.
• Proficiency in low-power design methodologies using UPF.
• Work with Foundry and standard cell IP vendors to define signoff methodologies and validate/adjust them based on feedback from Post-Silicon Validation teams.
• Experience in using AI tools to improve productivity.

Requirements

• Bachelor’s Degree in Electrical Engineering with 8+ years of Physical Design experience or Master’s Degree in Electrical Engineering with 6+ years of Physical Design experience or PhD in Electrical Engineering with 3+ years of Physical Design experience.
• Experience with RTL2GDSII flow and design tapeouts in 7nm/5nm/3nm or below process technologies.
• Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus, or Calibre/Pegasus.

Preferred Qualifications

• Experience working on Full-chip activities, including floor-planning, power-grid planning, partitioning, and pin-assignment.
• Experience with hierarchical design, timing closure, physical design convergence, and power integrity analysis.
• Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
• Experience with custom clock (H-Tree or Mesh) at chip level.
• Experience with Python and usage of AI tools by giving accurate prompts.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era—and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across their entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. We work as a team, collaborating with empathy to make really big things happen on a global scale.

Pay

The starting salary range for this position is $183,800.00 to $263,600.00 for new hires in U.S. and/or Canada locations, not including incentive compensation, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. Below are the full salary ranges for specific locations:

• New York City Metro Area: $183,800.00 - $303,100.00
• Non-Metro New York State & Washington State: $163,600.00 - $269,800.00

For quota-based sales roles, the ranges include base pay and sales target incentive compensation combined.

Benefits

• Medical, dental, and vision insurance.
• 401(k) plan with a Cisco matching contribution.
• Paid parental leave, short- and long-term disability coverage, and basic life insurance.
• Eligibility for grants of Cisco restricted stock units, which vest following continued employment.
• Paid time off:
  • 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees.
  • 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness.
  • Non-exempt employees receive 16 days of paid vacation time per full calendar year, accrued at 4.92 hours per pay period.
  • Exempt employees participate in Cisco’s flexible vacation time off program with no defined limit (subject to business limitations).
  • 80 hours of sick time off provided on hire date and each January 1st thereafter, with up to 80 hours carried forward annually.
  • Additional paid time away may be requested for critical or emergency family issues.
  • Optional 10 paid days per full calendar year to volunteer.
• Annual bonuses for non-sales roles, subject to Cisco’s policies.
• For sales roles, performance-based incentive pay split between quota and non-quota components:
  • Quota-based incentive pay:
    • 0.75% of incentive target for each 1% of revenue attainment up to 50% of quota.
    • 1.5% of incentive target for each 1% of attainment between 50% and 75%.
    • 1% of incentive target for each 1% of attainment between 75% and 100%.
    • Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap.
  • Non-quota-based sales performance elements may pay 0% up to 125% of target.

Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.