Analog IP Design Execution Manager

About the role

The Hard IP and Test Chip Development team, within Intel's Central Engineering Group, is responsible for delivering industry defining analog and mixed signal Intellectual Property (IP) for Intel's Client, Datacenter, AI and Foundry customers. The IO team owns high-speed serial IO and die-to-die interfaces across multiple advanced process nodes.

Responsibilities

• Lead technical teams to deliver IP that will shape Intel's future of IO and chiplet interconnect technology.
• Coordinate across IP domains (architecture, analog, logic, validation) and key SOC swim lanes to deliver IP releases on time and with committed content and quality.
• Identify technical problems and take the lead to drive solutions.
• Ensure appropriate progress against schedule, recommend recovery actions and mitigate issues.
• Drive efficient, effective, and transparent decisions to keep IP execution tracking positively toward aggressive and achievable deliverables.
• Communicate clearly and appropriately to a range of audiences spanning engineers, technical leaders, and executives.
• Establish productive, collaborative relationships with peers, partners, and stakeholders spanning SOC, IP design, and post-silicon validation teams.
• Conduct retrospective reviews to drive continuous improvements in execution efficiency and product quality.
• Inspire people, role model Intel values, develop the capabilities of others, and ensure a productive work environment.

Qualifications

• Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field with 8+ years of experience.
• 5+ years of experience managing technical execution for silicon projects.
• Solid foundational knowledge of analog design principles-noise, jitter, matching, stability, and linearity.
• Experience in analog design and IP delivery.

Preferred Qualifications

• Master's degree in Electrical Engineering, Electronics Engineering, or related field with 6+ years of experience.
• 8+ years of experience managing technical execution for silicon projects.
• Proven expertise in analog IP development and delivering from concept to launch with hands-on experience in analog circuit design, mixed signal logic and validation, physical design.
• Experience in silicon bring-up, post-silicon validation, and lab debug of analog circuits.
• Deep knowledge of high speed serial IO technologies such as PCIe/CXL and USB and of die to die technologies such as UCIe, BoW, HBM.

Pay

$190,610.00 - 269,100.00 USD

Schedule

Shift 1 (United States of America)

Location

US, Arizona, Phoenix