Senior Analog IP Integration, Power, and SI Engineer

About the role

The Hard IP and Test Chip Development team, within Intel's Central Engineering Group, is responsible for delivering industry defining analog and mixed signal IP for Intel's Client, Datacenter, AI and Foundry customers. The IO team owns high-speed serial IO and die-to-die interfaces across multiple advanced process nodes. We are seeking an experienced Analog Design Engineers to join our engineering team.

Responsibilities

• Design and simulate analog and mixed-signal circuits including amplifiers, data converters, voltage regulators, PLLs, and other analog building blocks.
• Develop circuit architectures and perform detailed transistor-level design.
• Create and optimize layouts working closely with layout engineers.
• Perform circuit analysis, simulation, and verification using industry-standard tools (Cadence, Synopsys, etc.) using approaches that enable automation and take advantage of available AI-supported solutions.
• Lead analog design projects from specification to silicon validation.
• Mentor junior engineers and provide technical guidance.
• Collaborate with cross-functional teams including architecture, logic, verification, physical design, layout, post-silicon manufacturing and validation teams, and SOC partners.
• Facilitate design development and convergence across global teams designing concurrently in numerous process nodes.
• Develop test plans and oversee silicon characterization.
• Debug and resolve design issues during pre and post-silicon phases.
• Optimize designs for performance, power, and area requirements.
• Ensure designs meet specifications and industry standards.

Qualifications

• Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field with 5+ years of experience in analog/mixed-signal circuit design for high-speed SerDes or similar applications.
• Proven experience in one or more of the following areas: PLL, CDR, CTLE, DFE, ADC, RX AFE, Transmitter (TX), Power Delivery design, IP floor planning, IP top level performance simulation, signal integrity analysis.
• Background in high-speed IO calibration and training algorithms.
• Familiarity with high-speed communication standards such as UCIE and PCIe (Gen5/Gen6/Gen7).
• Core analog design principles, including noise, linearity, matching, and stability.
• Hands-on experience with advanced FinFET CMOS process technologies.
• Analog design and simulation tools such as Cadence Virtuoso/ADE, HSPICE, or equivalent.
• Post-silicon validation, lab measurements, and debug of analog circuits.

Preferred Qualifications

• Master's degree in Electrical Engineering, Electronics Engineering, or a related discipline with 4+ years of experience in analog design for high-speed SerDes and/or die-to-die applications.
• Power Delivery design, IP floor planning, IP top level performance simulation OR signal integrity analysis.
• Exposure to next-generation high-speed standards such as PCIe 6.0, 800G Ethernet, or JESD.
• Experience with Verilog-A modeling, MATLAB simulations, and automation scripting (e.g., Python, Tcl).
• Strong understanding of signal integrity concepts, channel modeling, and system-level link analysis.
• Background in standard and advanced package technologies.