Analog IP Design Execution Manager

About the role

The Hard IP and Test Chip Development team, within Intel's Central Engineering Group, is responsible for delivering industry defining analog and mixed signal IP for Intel's Client, Datacenter, AI and Foundry customers. The IO team owns high-speed serial IO and die-to-die interfaces across multiple advanced process nodes.

Responsibilities

• Lead technical teams to deliver IP that will shape Intel's future of IO and chiplet interconnect technology.
• Coordinate across IP domains (architecture, analog, logic, validation) and key SOC swim lanes to deliver IP releases on time and with committed content and quality.
• Identify technical problems and take the lead to drive solutions.
• Ensure appropriate progress against schedule, recommend recovery actions and mitigate issues.
• Drive efficient, effective, and transparent decisions to keep IP execution tracking positively toward aggressive and achievable deliverables.
• Communicate clearly and appropriately to a range of audiences spanning engineers, technical leaders, and executives.
• Establish productive, collaborative relationships with peers, partners, and stakeholders spanning SOC, IP design, and post-silicon validation teams.
• Conduct retrospective reviews to drive continuous improvements in execution efficiency and product quality.
• Inspire people, role model Intel values, develop the capabilities of others, and ensure a productive work environment.

Requirements

• Strong results orientation and great aptitude for problem-solving.
• Ability to see a challenge on the horizon and plan for it.
• Facilitating direct and open communication.
• Natural and ready collaboration with a wide range of contributors: technical leads, manager peers, partner teams, senior technologists, executives, and other organizations.
• Articulating ideas and key messages succinctly.
• Demonstrated success leading large-scale, cross-functional programs with aggressive timelines and complex external dependencies.
• Ownership mindset with a high degree of urgency and accountability for execution results and customer success.
• Solid understanding of the end-to-end silicon lifecycle, from architectural definition through production qualification and release.
• Familiarity with AI/ML-driven design productivity techniques, automation frameworks.
• Proven experience executing complex mixed-signal and/or high-speed serial IP development in advanced semiconductor process nodes.
• Excellent communication, documentation, and presentation skills to audiences ranging from individual contributors to technical leaders and executives.

Qualifications

• Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field with 8+ years of experience.
• 5+ years of experience managing technical execution for silicon projects.
• Solid foundational knowledge of analog design principles-noise, jitter, matching, stability, and linearity.
• Experience in analog design and IP delivery.