UVM Lead Verification Engineer

About the role

This position requires a candidate with extensive experience in System Verilog/UVM for unit/module level verification, including lead design verification team management.

Responsibilities

• Lead a team of 5 or more verification engineers in designing and implementing UVM testbenches from scratch.
• Develop and integrate VIPs and bring up existing Verilog/VHDL environments into UVM-based environments.
• Plan tests, write coverage-critical code, and debug complex issues.
• Show deep knowledge of AMBA protocol.

Requirements

• Fine-grained experience in System Verilog/UVM for unit/module level verification.
• Experience leading a team of verification engineers.
• Strong background in developing UVM testbenches from scratch.
• Experience integrating VIPs and bringing up Verilog/VHDL environments into UVM-based environments.
• Deep knowledge of AMBA protocol.

Qualifications

The ideal candidate will have a strong academic background in computer engineering or a related field, with a focus on verification methodologies.

Skills

• System Verilog/UVM proficiency.
• Experience with AMBA protocol.
• Leadership and team management skills.
• Test planning and debugging abilities.

Benefits

Comprehensive benefits package including health insurance, retirement plans, and paid time off.

Pay

USD $170k annually.

Schedule

Full-time position.